The LAN9218 has been designed to provide the highest performance possible for any given architecture. It is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant and includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers.
LAN9218 includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the memory buffer architecture allows the most efficient use of memory resources by optimising packet granularity. Dropped packets are eliminated as the buffer memory can store 200 packets and automatic or host-triggered PAUSE and back-pressure flow control are supported.
The LAN9218 offers a variety of power management and wake-up features. The LAN9218 can be woken up from reduced power mode by a number of methods including “Magic Packet”, “Wake-on-LAN” and “Link Status Change”.
The chip comes in a lead-free, low profile 100-pin TQFP package. It operates from a single 3.3V power supply and has 5V tolerant I/O.