Up to 264Mbytes/s of internal data bandwidth permits high data bus throughput and an optimised 3-stage pipeline deliver high computational throughput. The tightly coupled, on-chip SRAM gives single clock access from the pipeline and high speed interrupt servicing simplified real-time event programming. Most instruction, data access and instruction-fetch commands are carried out within a single clock cycle. The rich instruction set of 220 instructions, and a mixed 16-bit and 32-bit instruction set architecture, facilitate high code density and minimise memory requirements.
Tool support includes from Atmel includes the AVR32 GNU tool chain, IwIP TCP/IP protocol stack and the AVR32 Studio – a multiplatform integrated development environment. A suitable C Compiler is the Embedded Workbench from IAR Systems.