The drivers use smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits.
The SGD architecture also optimises dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors.
Optional integrated current shunt amplifiers support different motor control schemes and a buck regulator powers the gate driver or external controller.
A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events.
The DRV835x drivers are supported by the DRV8353Rx-EVM driver evaluation modules — 15A, three-phase BLDC drive stages based on either the DRV8353RH or DRV83583RS gate driver and TI CSD88599Q5DC NexFET power blocks.
The evaluation modules features individual DC bus and phase voltage sense as well as individual low-side current shunt amplifiers, making it ideal for sensorless BLDC algorithms.