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IBM unveils world’s first sub-1nm chip technology

IBM unveils world’s first sub-1nm chip technology

IBM unveils world’s first sub-1nm chip technology IBM unveils world’s first sub-1nm chip technology

IBM has unveiled a major semiconductor breakthrough with the introduction of the world’s first sub-1 nanometre chip technology, featuring a transistor architecture at the 0.7nm, or 7 angstrom node.

The achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

IBM’s new sub-1nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM’s three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions.

Published technical results report the new chip is projected to offer a substantial leap in capability – up to 50% more performance, or 70% greater energy efficiency than IBM’s 2nm node chips – supercharging compute for applications ranging from Generative AI and Cloud infrastructure to next-generation electronic devices.

“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometre era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”

“Think about AI computing – everyone demands more performance, but no one wants to pay for the bill for the power … This new innovation will deliver the higher performance … 50% compared to what’s best available chip today … At the same time, it can reduce the power by 70% if you choose to manage your power in that computing, which is very critical for AI,” said Huiming Bu, Vice President, Silicon Technology Research & Development.

To produce this chip, IBM researchers developed an entirely new transistor architecture, called ‘nanostack’, the industry’s first known three-dimensional, nanosheet-based design. Nanostack represents a major advance beyond nanosheet technology, the industry’s current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimising performance and power efficiency of each transistor independent of the other.

IBM’s nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation. Additionally, in new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40% scaling in SRAM, unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads.

With this structure, logic technology can extend for the first time below the 1nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7nm technology – also referred to as 7 angstroms – demonstrates how continued scaling remains possible. With the new nanostack architecture, IBM’s semiconductor roadmap projects at least a decade of future scaling.

With the expectation of the earliest adoption of nanostack technology at the sub-1nm node, IBM sees a path to production in as early as the next five years.

“If you look at the history of the two nanometres and how that has become the industrial standard, our expectation is this is the same. This is the next jump in technology,” said Gambetta.

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