The VIP models feature direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.
All leading third party simulators, verification languages and methodologies are supported by the model. This enables SoC verification teams to verify the correctness of interfaces to these specialised memories, using their chosen method.
Robert Feurle, Vice President, Compute and Networking Marketing, Micron, said: “Memory is a critical factor in increasing functionality and performance of advanced system topologies. The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as HMC.”
“3D memories are increasingly becoming essential to the next gen of electronic products,” added Erik Panu, Vice President, Research & Development, IP Group, Cadence. “The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs.”
