Full scale 3D simulation of statistical variability associated with metal gate granularity and the corresponding metal work function variations have been carried out to clarify the magnitude of statistical variability in 32nm CMOS transistors with high-k/metal gate stack. For these devices the metal granularities can double the variability if the metal grain size becomes comparable to the transistor dimensions.
Also, a full statistical characterization of an ARM926 core has been achieved. A correlation between the timing, leakage and dynamic power has been demonstrated on local (within die) and non-local (above die) variations. The traditional corner analysis could be benchmarked with innovative statistical analysis techniques. Using the ARM core as driver, REALITY has confirmed that the SRAM components are responsible for more than the half of the variations on critical path timing. Hence, Statistical Timing Analysis (SSTA) flows that assume predictable timing response from these components may lead to over-optimistic conclusions. For that purpose REALITY has deployed a holistic statistical characterization flow including SRAM analysis.
With a novel flow integrating manufacturing variations and ageing effects for mixed-signal circuits, the REALITY project also developed a CAD environment that allows designers to make more accurate estimations and thus make circuits more energy and cost efficient.
Finally, REALITY evaluated the impact of process variation in SW-level metrics showing process variability is not only a concern for HW but for SW as well. Variability affecting multi-core multimedia platforms makes it hard to guarantee a certain QoS from the running application’s functionality. For that purpose, different circuit design techniques for system adaptation have been investigated, among them Adaptive Body Biasing (ABB). REALITY has shown that ABB can speed up a system-on-chip when due to technology parameter variations the manufactured product became too slow.