Lattice Diamond 1.3 software now provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device. Furthermore, simulation files can be implemented, if required. The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator.
In addition, the synthesis design constraints flow is now more intuitive and allows for multiple files that can be managed similar to the back-end preference files. And, when using the Reveal™ Analyzer, Lattice Diamond’s on-chip debugger, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
Lattice Diamond 1.3 software is also now integrated with Lattice’s PAC-Designer® 6.1 mixed signal design tools, providing design support for Lattice’s programmable mixed signal Platform Manager™ devices. This means that the digital control functions in Verilog or VHDL within the Platform Manager can be implemented directly with Lattice Diamond 1.3.