In addition, IDT continues to help drive the development of the RDIMM ecosystem by providing the DDR3 industry with a standardized validation platform known as the Register Validation Board (RVB). The RVB will allow all members of the DDR3 ecosystem to test, debug, and validate DDR3 Register-DIMMs on a standardized platform. Moreover, the RVB enables the DDR3 community to self-validate the functionality of each of their RDIMM designs, and will further help speed the adoption of DDR3 RDIMMs. The IDT RVB will be available for the DDR3 industry through the JEDEC standards body.
The integration of the register and PLL into a single device enables RDIMM vendors to develop a simplified design and board layout. In addition, the 74SSTE32882 supports an internal PLL feedback loop to reduce trace routing and spread spectrum clocking to reduce EMI. The supply voltage for the 74SSTE32882 is reduced to 1.5V, limiting power consumption and heat generation. These features are valuable to RDIMM vendors because they enable significant cost savings through the reduction of board real estate and the elimination of external components.
The IDT 74SSTE32882 is designed to be fully compatible with the most current JEDEC specification. The guideline set by JEDEC ensures interoperability for all JEDEC compatible DDR3 solutions and will help facilitate the growth of the DDR3 market.