“The ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry,” said the author of the new eBook, Kent Zetterberg, product manager, ASSET InterTech. “Because DDR3 memory chips have become so prevalent in high-speed systems, I used this technology as the basis for explaining how JTAG or boundary-scan methods can be integrated into every step of a system’s life cycle, beginning in design and transitioning into manufacturing and field service.” The ebook is titled Testing DDR3 Memory with Boundary Scan / JTAG and it is available from the Asset Intertech website.
eBook Addresses DDR Memory Test Problems
ASSET InterTech has published a new eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. A recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory soldered to circuit boards is a major problem for system manufacturers.