Keithley Instruments has published Parallel Test Technology: The New Paradigm for Parametric
Testing, a semiconductor parametric test handbook. The 60-page handbook offers an overview of the emerging test technique known as parallel parametric testing, a strategy for wafer-level parametric testing that uses concurrent execution of multiple tests on multiple scribe line test structures and helps semiconductor fabs maximize their test throughput and reduce their cost of test.
The handbook covers:
The basics of parallel parametric test
The parallel test implementation process
Applying parallel parametric test to existing hardware setups
Test structure design for parallel testing
Keithley’s Parallel Test Technology handbook also contains a section with sample programming code for a typical parallel test setup using pt_execute, and a glossary of common parallel parametric test terminology.