Following industry demands, JTAG Technologies has developed the new boundary-scan controller to satisfy the burgeoning requirements for high-speed In-System Programming (ISP) of flash memories and CPLDs – plus complex digital circuit testing. The DataBlaster JT 37×7/PCIe offers the user sustained test clock speeds of up to 40MHz by use of JTAG Technologies’ proprietary ETT™ (Enhanced Throughput Technology) system and features a flash image buffer memory which may be expanded to 128Mbits.
Supplied with the complementary QuadPOD, also from JTAG Technologies, the DataBlaster JT 37×7/PCIe offers four synchronised TAPs (Test Access Ports) able to support multi-TAP test targets (i.e. Units Under Test – UUT) or the gang programming of four single TAP targets. QuadPOD™ is ‘low-voltage ready’ and the advanced technology also allows maximum test speeds at the target by incorporating high-speed signal conditioning, logic threshold adjustments and cable delay compensations in a compact, remote, extension module.
The scalable DataBlaster JT 37×7/PCIe range starts with the low-cost entry model JT 3707/PCIe, ideal for high-speed 40MHz test applications and in-system PLD programming. Companion models JT 3717/PCIe and JT 3727/PCIe, optionally fitted with an ETT module for flash ISP, support high-throughput flash programming as well as test and PLD programming. The flexible nature of ETT allows it to support memories with various data-bus widths from 1bit to 64Kbit.
DataBlaster/PCIe units are fully compatible with all revisions of JTAG Technologies’ test and ISP tools, such as JTAG ProVision and the former ‘Classic’ family of development and run-time packages.