As a result, design and verification of electronic warfare systems and massive-MIMO systems for 5G is accelerated, which in turn enables faster deployment.
The newly integrated FPGA design flow enables system architects and FPGA engineers to download custom algorithms into Agilent digitizers with on-board FPGAs using built-in template designs and intellectual property cores with automatic push-button programming. The pre-defined FPGA interface template makes it easy to co-simulate real-time custom algorithms in the FPGA and top-level system modelling.
The W1462 SystemVue FPGA Architect is part of the SystemVue simulation environment, Agilent’s premier platform for electronic system-level design.
Updates include flexible hardware design entry with custom HDL and graphical schematic drawing using high-abstraction-level, primitive fixed-point blocks, vendor-agnostic HDL code generation and third-party HDL co-simulation and a fully optimized and automated hardware implementation flow for leading-edge, high-performance digitisation.