The de-emphasis technique is used in the transmission of digital electrical signals at gigabit data rates. De-emphasis is a signal pre-distortion to compensate for signal degradations that occur when transmitting electrical signals with gigabit rates over PC board traces, backplanes or long cables.
Agilent’s new de-emphasis signal converter, the N4916B, allows users to emulate transmitter de-emphasis with one pre- and two post-cursors, as well as individually adjust de-emphasis levels up to 12.0 dB. With its DC-coupled outputs, the signal converter tolerates even unbalanced pattern streams. The N4916B is transparent to jitter, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. Agilent’s new de-emphasis signal converter can be used as front-end for J-BERT N4903A/B, ParBERT or other gigabit pattern generators.
Besides its de-emphasis capabilities, the N4916B offers a unique clock-doubling option, which enables error, jitter and eye analysis with J-BERT N4903B of transmitters using half-rate clocks.
Ultraflexible SSC Injection
The spread spectrum clocking (SSC) injection is becoming more common for high-speed interconnects. SSC modulates the operating frequency of a circuit slightly to spread its radiated emissions over a range of frequencies.
J-BERT N4903B’s SSC option now provides more flexible and arbitrary SSC injection capabilities that can be combined with sinusoidal jitter injection, helping R&D engineers emulate worst-case and real-world SSC conditions, especially for SATA, SAS and USB3 receivers.
SATA ISI Channel
The new Agilent SATA ISI Channel N4915-60001 helps R&D and test engineers easily reproduce precise SATA compliant stress conditions for the receiver stress test when used in combination with J-BERT N4903B.
We are very proud to offer the industry’s leading jitter tolerance test solution, said J�rgen Beck, general manager of Agilent’s Digital Photonic Test product line. By adding multitap de-emphasis, ultraflexible SSC and SATA ISI channel, we significantly simplify the accurate characterization of the next-generation of serial interfaces operating above 5 Gb/s. With this introduction we confirm our commitment to enable R&D and validation teams to release robust high-speed digital interfaces for the next generation of computer, consumer and communication devices.