New generation 28nm SpRAM generator for optimised power consumption
It requires true differentiating factors when launching any low-power SoC on a highly competitive market. For IoT applications requiring ultra-low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimise power modes by partitioning the SoC.
This will minimise dynamic power in active modes, as well as power leakage in standby modes. Dolphin Integration is on a continuous quest to provide new solutions to its customers, to help them address their challenges.
Dolphin Integration has therefore, announced the availability of the Calypso architecture. Calypso is a SpRAM optimised for low power SoCs in TSMC 28nm HPM technology.
This Single-port SRAM is designed to optimise power consumption, with gains between 20 and 30% compared to alternative solutions in 28nm.
The SpRAM Calypso reaches such a performance thanks to its data retention mode, with a memory core lowered to 0.63 V. This minimum voltage retention feature allows leakage to be divided by between two and ten (depending on memory size) compared to other memory compilers in stand-by mode.
SpRAM Calypso is part of a 28nm HPM portfolio:
- Ultra high-density 6-track standard cell libraries,
- Cache controller, R-Stratus-LP, both improving speed and reducing power consumption by up to three times, compared to stand-alone eFlash memory,
- InnovativeMAESTRO, a fabric IP making the implementation of the Activity Control Unit of a low-power SoC easy and safe.
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