Navitas’ new 650V MPS SiC power diodes

Navitas Semiconductor has announced the fifth generation of high-speed GeneSiC SiC power diodes for demanding data centre, industrial motor-drive, solar and consumer applications.

The 650V-rated Merged-PiN Schottky (MPS) diodes integrate a unique PiN-Schottky structure, delivering ‘low-built-in voltage-biasing’ (‘low knee’) for the highest efficiency across all load conditions with superior robustness. Applications include PFC in server/telecom power supplies, industrial motor drives, solar inverters, LCD/LED TVs, and lighting. 

“We’re delivering reliable, lead-Edge performance for in-demand applications like AI and ChatGPT data centre power,” noted Dr. Ranbir Singh, Navitas EVP for SiC. “Efficient, cool, dependable operation ensures long lifetimes and brings peace-of-mind to power designers and optimises their time-to-prototype and time-to-market.” 

The novel GeneSiC MPS design combines the best features of both PiN and Schottky diode structures, producing the lowest forward-voltage (VF) drop of only 1.3V, high surge-current capability (IFSM), and minimised temperature-independent switching losses. Proprietary thin-chip technology further reduces VF and improves thermal dissipation for cooler operation. These GeneSiC diodes are being offered in a low-profile surface mount QFN package for the first time. 

To ensure reliable operation in critical applications, the gen-5, 650V MPS diodes offer best-in-class robustness and ruggedness, with high surge-current and avalanche capability, with 100% avalanche (UIL) production testing. 

Ranging from a 4-24A capability, in an array of surface-mount (QFN, D2-PAK) and through-hole (TO-220, TO-247) packaging, the GExxMPS06x-series MPS diodes cover applications ranging from 300 to 3,000W and diverse circuits such as solar panel boost converters, and continuous-current mode power factor correction (PFC) in gaming consoles. With a ‘common-cathode’ configuration, the TO-247-3 package offers great flexibility for high power density and bill-of-material reduction in interleaved PFC topologies.

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