Mixed Signal/Analog

Simulator improves performance speedup on mixed-signal design

13th October 2017
Alice Matthews

In order to accelerate ASIC development for delivery of its automation equipment for test and industrial applications, Cadence Design Systems has announced that Teradyne has standardised its simulation tasks using the Xcelium Parallel Logic Simulator. With the Xcelium simulator, Teradyne achieved a two times performance speedup with production-use single-core, mixed-signal ASIC verification when compared with its previous simulation solution.

Teradyne, a longtime user of the broader Cadence Verification Suite, built a verification environment that can deliver first-pass silicon success with mixed-signal designs, accelerating time to market. The Xcelium simulator has quickly become a key component in the verification environment, providing the Teradyne team with an easy-to-use solution that delivers fast simulation performance and ensures high-quality designs.

With Teradyne’s extensive use of real number models, the Xcelium simulator allows its designers to perform earlier, more complete full-chip mixed-signal verification. In addition to using the Xcelium simulator, Teradyne is also utilising the Cadence JasperGold Formal Verification Platform to assist with formal-first verification and expedited debug, and the Cadence vManager Metric-Driven Signoff Platform to effectively integrate the verification process from planning to metrics management across formal, simulation, emulation and verification IP.

“Rapid development and verification of our automation test equipment solutions is critical to our success,” said Andre Hendarman, Director of Mixed Signal ASIC Development at Teradyne. “The Xcelium Parallel Logic Simulator has provided us with the fastest simulation performance by far, which is helping us speed up the delivery of our test products, while also ensuring our designs are of the highest quality.”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

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