A low noise floor of -157.6 dBFS and a large signal spurious-free dynamic range (SFDR) performance exceeding 85 dBFS, typical, allow low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the interface to external driving circuitry, while preserving performance of the ADC.
The device is suited for military radar and communications, multimode digital receivers (3G or 4G), test and instrumentation, and smart antenna system applications.