It is optimised for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block.
The analogue input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs).
Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting divide-by-factors of two, four and eight.
The AD9684 is suitable for a range of applications, including communications, diversity multiband/multimode digital receivers (LTE, 3G/4G, TD-SCDMA, W-CDMA, MC-GSM), general-purpose software radios, ultra-wideband satellite receivers, instrumentation (spectrum analysers, network analysers, integrated RF test solutions), radar, digital oscilloscopes, high-speed data acquisition systems, DOCSIS CMTS upstream receiver paths, and HFC digital reverse path receivers.