Mixed Signal/Analog

Fujitsu Launches Ultrafast 56GSa/s 8-Bit ADC Technology

27th January 2009
ES Admin

Fujitsu has announced the availability of its new ultrafast ADC IP based on the revolutionary CHArge-mode Interleaved Sampler technology (CHAIS) for use in its standard 65nm CMOS process technology. This new high-speed ADC technology provides breakthrough performance levels in a standard CMOS process, enabling the integration of multiple ADCs with tens of millions of gates of signal processing logic and memory on a single chip. Initially targeting use in coherent receivers for 100G optical transmission, the technology is also applicable to high-end test equipment and any other system requiring high-speed data conversion and processing.

The new CHAIS technology provides previously unachievable combinations of sampling rate, resolution and power consumption. These circuits avoid many of the limiting factors, such as restricted bandwidth and poor linearity, of conventional architectures to make ADCs with sampling rates of up to 100GSa/s feasible in CMOS for the first time.

Power consumption for the ADC is 2W typical per channel at 56GSa/s, which is unheard of for this performance level (ENOB>6) – a half-speed mode provides 28GSa/s at 1W per channel. A 1.75GHz input reference clock is internally multiplied to provide ADC sampling clocks with less than 100fs total rms jitter and less than 500fs I/Q ADC skew.

“With our new ADC technology in combination with the ability to integrate in excess of 50 million logic gates, we provide the enabling technology for upcoming telecom applications, such as 100G Ethernet and OTU-4”, said Dirk Weinsziehr, Vice President of Marketing and Development at FME. “Based on this technology our customers can build bespoke products with lower power consumption, higher integration and a unique manufacturability to secure their leading position in the market.”

The first production application of this breakthrough ADC technology will be a single-chip DP-DQPSK coherent receiver for 100G optical networks, with 4-channels of 56GSa/s 8-bit ADCs (I and Q signals, H and V polarisation) integrated with logic and memory to perform the complete receive PHY function when connected directly to the optical front-end.

A single-chip solution avoids the need to transfer terabits-per-second of data between ADC and DSP chips – reducing power consumption, silicon area and number of I/O pins. The need for expensive multi-chip module (MCM) technology is eliminated.

The increased ADC resolution and sampler dynamic range eases the design of the optical front-end by allowing part or all of the AGC function to be realised digitally after the ADC.

Continuous digital background self-calibration during operation means that external calibration test signals or non-volatile calibration memory are not required, and no user intervention is needed to achieve and maintain the specified performance levels.

“Current high-speed ADCs are mostly developed in a SiGe process technology. Products using such technology tend to suffer from high power consumption and limited integration with digital signal processing. We saw a strong demand from our customer base for high-performance data converters in standard CMOS technology,” explained Neil Amos, Director of the Communications Business Unit at FME. “With this groundbreaking ADC technology, Fujitsu now provides the option to integrate analogue conversion at GSa/s and digital signal processing on the same die. Originally driven by telecom applications we now see increasing interest in test and measurement and high-speed interface applications.”

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