Clocking ICs replace expensive high-frequency VCOs and save space

The AD9552 replaces larger, expensive, high-frequency VCOs (voltage-controlled oscillators), including OCXO (oven-controlled crystal oscillator), VCXO (voltage-controlled crystal oscillator) and TCXO

(temperature-compensated crystal oscillator) devices. The upconverter requires either a single-ended, low-frequency reference signal or a crystal reference to establish the higher output frequency the IC generates. It provides ultra-low jitter of under 0.5 ps (picoseconds) operating with input

frequencies in the range of 50 kHz to 80 MHz at half the price of competitive alternatives. The device can generate almost any desired output frequency up to 900 MHz for a variety of applications, such as HDTV, data acquisition, wireless basestations, test and measurement, networking and

telecommunications. The upconverter features very low power consumption-less than 400 mW in a compact 5 mm x 5 mm package size.



The AD9552 is a fractional-N, PLL- (phase-locked-loop) based clock

generator. The device employs a Σ-Δ (sigma-delta) modulator to accomplish

fractional frequency synthesis. The user supplies an input reference signal

by connecting a single-ended clock signal to the REF pin or by connecting a

crystal resonator across the XTAL pins. The AD9552 is pin-programmable,

providing one of 64 standard output frequencies from any of eight common

input frequencies. The device also has a 3-wire SPI interface, enabling the

user to program custom input-to-output frequency ratios. The AD9552 requires

only a 12-nF external capacitor to complete the PLL's loop filter. The

output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels.



AD9547: Next Generation Clock Synchronizer Offers 66 Percent Better Jitter

Performance, up to 100-times Narrower Loop Filters



The AD9547 is the next generation of the AD9549 - one of ADI's most popular

new clock devices in both the wired and wireless telecom markets. When

compared to the AD9549, the AD9547 boasts 66 percent better jitter, 100

times narrower loop-filter bandwidths (as narrow as 1 milliHertz) with twice

as many inputs and outputs, and it supports Stratum-2 level holdover. The

AD9547 also serves any application with remote equipment requiring

synchronization to local systems. It generates an output clock that

synchronizes to one of two differential or four single-ended external input

references saving designers time and money because they no longer need to

rely on additional clock distribution chips to complete their clock trees.



The AD9547 provides synchronization for many systems, including synchronous

optical networks (SONET/SDH). The digital PLL reduces input time jitter or

phase noise associated with the external references.



The AD9547 continuously generates a clean, low jitter, valid output clock,

even when all references have failed, by means of digitally-controlled loop

and holdover circuitry.