Low voltage operation, however, is still subject to process and temperature and other variations. To overcome the impact from these variations CSEM and MIFS applied a variety of design techniques and implemented Body-bias-based Adaptive Dynamic Frequency Scaling (ADVbbFS) as one of the key IPs.
A 32-bit RISC microcontroller designed in C55DDC was presented recently at IEEE CICC in Austin, TX, demonstrating only 2.5uW/MHz – a new world record in a 55nm CMOS process.
For Keizaburo Yoshie, Senior Vice President, MIFS: “Combining CSEM’s ULP design experience with MIFS’ DDC process technology helps realise IoT chip designs that are unbeatable in energy efficiency.”
Alain-Serge Porret, CSEM’s Vice President, Integrated and Wireless Systems, said: “Low voltage design is essential for the next generation of IoT devices; we were delighted to team up with MIFS to make this dream a reality.”
Ready for design integration
A complete design ecosystem is now available, including a process design kit (PDK) with all libraries and key analogue IP blocks.