Micros

Partnership Delivers Free Diamond Processors on Free Mask Charge ASICs

26th November 2007
ES Admin
Tensilica and eASIC Corporation have announced a partnership to remove the cost barriers for developing custom embedded System-on-a-Chip. (SoCs). Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and DSP cores for its free mask charge, no-minimum order ASICs. This unique combination enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume. Designers will now be able to develop customized, highly differentiated ASIC solutions at a lower cost than FPGA-based embedded systems.
Tensilica’s processors range from a very small, low-power 32-bit controller up to the industry’s highest performance digital signal processing (DSP) core and a multifunction audio processor that has been designed into millions of cellular phones.

The Diamond Standard family covers the broadest range of performance of any embedded computing architecture and the processors are supported by an optimized set of Diamond Standard software tools and an extensive ecosystem of industry infrastructure partners. The Diamond Standard family is available to eASIC’s customers via the company’s eZ-IP Alliance program.

“Free Tensilica processors on zero-mask charge structured ASICs is revolutionary breakthrough in reducing the upfront costs for customers looking to develop low-cost custom embedded processing systems at any volume,” stated Jasbinder Bhoot, Sr. Director, Marketing at eASIC Corporation. “This partnership is proof that a new era of system on a chip is upon us. No upfront cost and no minimum order quantity for an embedded processor core on a high-performance and volume-capable ASIC”

“Several of our customers have been attracted to eASIC’s Nextreme Structured ASICs for fast prototyping or mass production,” stated Chris Jones, Tensilica’s Director of Strategic Alliances. “eASIC’s Structured ASIC technology offers customers a lower power, higher density solution than FPGAs at a much lower cost and faster time to market than cell-based ASICs.”

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