Adding programmable logic blocks to MCUs

5th February 2015
Nat Bowers


Adding programmable logic blocks to MCUs offers some interesting benefits, as Sally Ward-Foxton discovers for ES Design magazine.

With the extension of its 8-bit PIC16 range, announced in November last year at electronica, the introduction of the PIC16F161X family from Microchip marked the strategic addition of programmable logic. Each member of the new family incorporates either two or four of Microchip’s Configurable Logic Cell (CLC) blocks, which are essentially small Programmable Logic Devices (PLDs). The CLCs are user-configurable to enable either combinational logic functions such as AND, OR, XOR or NOT gates, or even timers, flip-flops and latches. The idea is to implement some of these logic functions in integrated hardware rather than software; its a bid to eliminate some code overhead, and the functions being subject to software’s speed limitations. It also avoids the need for additional, external components, which would cost money and take up board space.

The CLCs are crucial to the use of the device’s Core-Independent Peripherals (CIPs), since they are used to connect the peripherals to each other without going through the core. Each CLC has up to 16 input signals, which may be a combination of I/O pins, internal clocks, other peripherals and register bits. Each CLC module has a single output that can drive an I/O pin, feed another CLC module or internal peripheral or can also trigger a rising or falling edge interrupt.

Lucio Di Jasio, MCU8 Business Development team, Microchip, explains that there are two important benefits to using programmable logic in an MCU like the PIC16 family: “Firstly, power consumption is reduced where the CLC is used to provide a smart wake-up of the processor. Secondly, CPU workload is reduced when the CLC is used to glue together multiple other peripherals to create entirely autonomous chains of events. These include also integration of digital and analogue features. Every time we use the CLC to automate a connection between peripherals and remove what otherwise would be an interrupt call, we are either reducing the CPU workload considerably or removing a hard timing constraint entirely. In both cases we can save power, reduce application complexity and ultimately save money.”

Di Jasio also explained that the CLC modules are completely asynchronous with the processor core, so they can be used while the core is in sleep or standby mode. This also means they can handle higher or lower clock speeds. Power consumption is optimised, while flexibility is maximised. The modules are small and low-power; enabling any of the CLC blocks produces no measurable increase in power consumption.

Making programming easy

Although the CLC modules incorporate some complex functionality, programming them needn’t be a time-consuming task. “Ease of use was always our number one objective,” Di Jasio says. “Configuring the CLC is made really easy using a visual tool that is available inside the MPLAB IDE.”

Block diagram for Microchip’s PIC16F161X family, showing up to four configurable logic cell blocks

Block diagram for Microchip’s PIC16F161X family, showing up to four configurable logic cell blocks

The PIC16’s CLC blocks can be programmed and reprogrammed on the fly, using Microchip’s specially developed CLC configuration tool. The tool is effectively a GUI which offers a series of setup options, and then depending on the options selected, outputs the required register settings in C or assembly language. This avoids having to program the CLC blocks directly using C or assembly language. It can also help to visualise the circuit’s behaviour. In practice, the most common use for the CLCs is glue logic - connecting other existing functions such as peripherals, as described earlier.

“CLCs provide an important internal form of glue logic that enables the application designer to create entirely new modules out of the other Core Independent Peripheral blocks,” Di Jasio says. “This is done at a relatively high conceptual level, in other words, the construction is not performed at the gate level (which would require a much higher level of complexity and specialisation) but rather at a peripheral level, using familiar elements like timers, PWMs, ADCs...  entirely within the comfort zone of most embedded control designers.”

The CLCs may also be used for re-routing signals without adding additional board layers; this can save space and money in designs. Examples of other applications include the implementation of synchronous gates, power sequencing and Manchester encoding. A pair of CLCs may also be combined to implement more complex logic functions, such as a data modulator.

One frequently encountered challenge that CLCs can help solve are glitches. A glitch is a signal which changes for less than the duration of one clock cycle; if it feeds multiple latches, some of them may switch, some may not. This kind of unpredictable behaviour is obviously to be avoided! They are particularly difficult to spot because propagation delays are temperature-dependent and therefore may not have been present when tested under different conditions in the lab. The CLC can be used to make a simple peripheral that eliminates glitches on clock signals (see Microchip App Note AN1451).

CLCs may also be used to create custom interfaces, such as the single-wire PWM signal required by a strip of LEDs. The PWM signal could be produced in software, but this is CPU-intensive and slow. Signals from other peripherals can be combined in the CLC to produce a composite peripheral that can drive the LED strip in a dozen lines of code (see Microchip App Note AN1606).

Asked about some more creative uses of the CLC modules, Di Jasio mentioned a case where the CLC was used to effectively turn another of the core independent peripherals upside down. The Numerically Controlled Oscillator (NCO) may be turned into almost its exact opposite, a PWM, but with the benefit of much higher resolution (see Microchip App Note AN1476). This is useful in some applications like dimming of LED lamps, where greater than 8-bit PWM resolution is required due to the sensitivity of the human eye.

“I keep being pleasantly surprised every time I discuss the CLC with a designer who has recently started using it,” Di Jasio adds. “It appears there is no end to the ideas and to the possible applications for this module. It is one of those things that makes you wonder, in hindsight... how is it possible we didn’t think of that before?”

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