Utilising novel split-gate technology to boost bit density

These attributes make this new cell design a promising candidate to surpass four bits per cell (QLC) for significantly higher memory density and fewer stacking layers. This technology was announced at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco, CA on December 11th.

3D flash memory technology has achieved high bit density with low cost per bit by increasing the number of cell stacked layers as well as by implementing multilayer stack deposition and high aspect ratio etching.

In recent years, as the number of cell layers exceeds 100, managing the trade-offs among etch profile control, size uniformity and productivity is becoming increasingly challenging. To overcome this problem, KIOXIA developed a new semicircular cell design by splitting the gate electrode in the conventional circular cell to reduce cell size compared to the conventional circular cell, enabling higher-density memory at a lower number of cell layers.

The circular control gate provides a larger programme window with relaxed saturation problems when compared with a planar gate because of the curvature effect, where carrier injection through the tunnel dielectric is enhanced while electron leakage to the block (BLK) dielectric is lowered.

In this split-gate cell design, the circular control gate is symmetrically divided into two semicircular gates to take advantage of the strong improvement in the program/erase dynamics. As shown in Figure 1 below, the conductive storage layer is employed for high charge trapping efficiency in conjunction with the high-k BLK dielectrics, achieving high coupling ratio to gain programme window as well as reduced electron leakage from the FG, thus relieving the saturation issue.

The experimental programme/erase characteristics in Figure 2 below, reveal that the semicircular FG cells with the high-k-based BLK exhibit significant gains in the program slope and program/erase window over the larger-sized circular CT cells.

The semicircular FG cells, having superior programme/erase characteristics, are expected to attain comparably tight QLC Vt distributions at small cell size. Further, integration of low-trap Si channel makes possible more than four bits/cell, e.g., Penta-Level Cell (PLC) as shown in Figure 3 below. These results confirm that semicircular FG cells are a viable option to pursue higher bit density.

Going forward, KIOXIA’s research and development efforts aimed at innovation in flash memory will include continuing Twin BiCS FLASH development and seeking its practical applications. At IEDM 2019, KIOXIA also announced six other papers highlighting the company’s intensive R&D activities in the area of flash memory.