Kilopass First to Demonstrate Antifuse Non-Volatile Memory IP With Successful Test Chips on TSMC 20nm Process

“We are extremely pleased that the silicon results from the TSMC 20nm test chips validated our antifuse NVM technology at this advanced process node,” said Harry Luan, CTO at Kilopass. “Our NVM IP cell arrays are designed to be compatible with Double Patterning Technology. Our successful experience on two generations of high-k metal gate processes gave us the know-how to successfully scale our NVM IP.”

As with the 28nm process experience, Kilopass NVM IP in the 20nm process achieved an operating window of over three decades between programmed and un-programmed cells. The Kilopass NVM IP also demonstrated excellent programmed cell current under different programming conditions.

Enabling our NVM IP on the latest TSMC 20nm gives us the lead position providing antifuse NVM IP, said Linh Hong, vice president of sales and marketing at Kilopass. Next generation SoC designs—network processors, baseband, application processors—that previously relied on external serial EEPROM and on-chip shadow SRAM to contain boot code, configuration data, and security keys are seeking to eliminate this combination in 20nm designs. Our NVM IP provides a more cost effective solution that will occupy the equivalent space of the on-chip shadow SRAM and most importantly will be available on the new 20nm TSMC process node. It will also eliminate the cost, power, and pads taken up by the external serial EEPROM.”

Kilopass NVM IP is now available for customer designs.