Achieving power savings of over 50%
The 28nm Fully-Depleted Silicon-on-Insulator (FDSOI) memory compiler has been launched by sureCore, and supports the company's low power, Single Port SRAM IP and Dual Port SRAM IP for 28nm FDSOI process technology. It also offers capacities up to 1MB with word lengths up to 288bits and supports 4, 8 and 16Mux factors.
The sureCore Single Port SRAM IP supports a wide operating voltage range of 0.6-1.2V and boasts dynamic power savings exceeding 50% of current commercial offerings. The IP also cuts static power by up to 35% with only a modest <10% area penalty.
The sureCore compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multi-plex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enhance and speed the design process.
“The availability of this new compiler marks a key milestone for sureCore and demonstrates that the power saving technologies we develop are now available to the SoC design community,” said sureCore’s Chairman, Guillaume d'Eyssautier. “This marks the start of a new era for low power electronics.”
sureCore’s silicon proven, 28nm FDSOI IP targets IoT and other applications that demand long battery life with minimal operating and standby power performance. The IP also provides value in the networking space where power and heat dissipation are critical.
In March, sureCore will follow the 28nm FDSOI compiler with a 40nm Ultra-Low power compiler that targets the leading foundry process. The company’s product roadmap also includes the introduction of a 40nm CMOS Ultra Low Power SRAM later next year. Work also continues on a 28nm CMOS solution.
“There is still considerable innovation happening at relatively mature production nodes,” said sureCore's CEO, Paul Wells. “With the growing IoT market, mature nodes such as 40nm are 28nm are taking on an extended life. Their cost performance is ideal for the IoT technical and business challenges.”