PCIe clock buffers reduce size and power consumption

24th July 2014
Nat Bowers

Expanding the company's PCIe timing portfolio, Integrated Device Technology has introduced what it claims to be the industry’s first 1.5V PCI Express (PCIe) buffer family. Operating from the same supply voltage as modern SoCs and FPGAs, the 9DBU buffers allow designers to use the same power rail. This reduces system complexity, physical size, and power consumption.

Offered in 2-9 output configurations to address PCIe applications, the 9DBU family operates from a 1.5V supply. This results in the industry’s lowest power consumption for PCIe timing devices, with eight-output devices using just 40mW. This reduces cooling requirements and lowers operating costs. The buffers support both non-PLL fan out and PLL zero-delay-buffer modes.

External or internal terminations are available, enabling designers to choose maximum flexibility with external termination circuitry or maximum space savings with internal terminations. The 9DBU buffers are compliant with PCIe Gen 1, 2, and 3 to increase flexibility and compatibility for designers.

Dave Shepard, Vice President and General Manager, Timing and RF, IDT, commented: “IDT has consistently led the timing industry in both performance and power, and the latest family of devices furthers our leadership position. SoCs and FPGAs are moving to lower supply voltages and IDT is extending its PCIe timing solutions portfolio to address this trend. Our 1.5V solutions take advantage of the low-voltage power savings, while simultaneously enabling customers to consolidate power rails to reduce the complexity of their systems. The timing solutions complement IDT’s V-series of 1.8V PCIe clocks for communications, computing and consumer markets.”

Available in standard VFQFPN packages from 4x4 to 6x6mm, the 9DBU buffers are sampling to qualified customers now.

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