Clock-frequency synthesisers configure automatically
Featuring jitter as low as 64fs RMS maximum, these synthesisers are designed to be placed adjacent to a switch, ASIC, FPGA, or PHY that requires several reference clocks with less than 100fs maximum jitter performance.
Additionally, the high-performance devices can be used as an adjustable OTN clock reference for OTU3/OTU4 mappers, as well as a reference clock for programmable fibre optic modules.
Consisting of the RC22504A synthesiser and RC32054A jitter attenuator and synthesiser, the devices can also act as a DCO for frequency margining or OTN clock applications.
A PLL core consists of fractional-feedback analogue PLL (optionally steered by a digital PLL in the RC32054A device) and operates from a crystal with frequencies between 25 MHz to 80 MHz.
The FemtoClock2 synthesisers feature four differential or eight LVCMOS outputs, supporting any frequency from 10 MHz to 1 GHz (180 MHz for LVCMOS).
The versatile synthesisers can configure themselves automatically after reset, using an internal customer-definable one-time programmable memory with up to four different configurations.
The FemtoClock2 synthesisers are supported by the RC22504A evaluation kit.
Engineers can develop configurations using Renesas RICBox software and then upload to the evaluation board using a USB connection.
The evaluation kit features Renesas low-noise power supply regulators and a Renesas low-noise fan-out buffer.