Reference design simplifies optical Ethernet implementation
Enabling engineers to quickly implement optical Ethernet designs up to 100Gbps, Lattice Semiconductor has released a reference design for IEEE 802.3 Management Data Input/Output (MDIO) interface controllers. RD1194 allows designers to implement a simple Wishbone user logic interface that enables the user to access the PHY registers.
The reference design utilises the MachXO3 family or the ECP5 family. Lattice claims that MachXO3 is the world’s smallest and lowest cost per I/O programmable platform and that ECP5 features the industry’s highest functional density with up to 85k LUTs and SERDES in tiny 10x10mm packages. The small size and low power of these FPGAs make them suitable for implementing I/O expansion, bridging or connectivity required to deliver Multi gigabit Ethernet applications, such as CFP2/4 modules, chip-to-chip communications and voltage level translation.
The RD1194 reference design supports MDIO IEEE 802.3 Clause 45/22 master/slave controllers, features pre-amble pattern selection through the input port and can be used to off-load the multiport CFP2/4 management from the main data path devices.
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