The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE or Aurora backplane connections. General purpose I/O signals, e.g. for trigger, are routed to the front panel that also contains 8 LED/Bi-colour.
ADC and DAC have a common sampling clock, which can be fed from front panel (Direct RF Clock) or from PLL locked to a 10/100MHz reference clock sourced from front panel or backplane. Sampling clock selection is by ordering option.
The VPX570 includes platform health management/monitoring capability using VadaTech’s field-proven tier 2 platform management software. An on-board management controller has the ability to access board sensors and manage FPGA image updates.
The unit is also available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.