FPGAs

FPGAs for edge computing use digital full flow solution

15th June 2020
Alex Lynn

Cadence Design Systems has announced that Efinix successfully utilised the Cadence digital full flow solution to complete the first wave of its Trion family of field programmable gate arrays (FPGAs), which are used in edge compute, AI/ML and vision processing applications for the mobile, industrial and surveillance markets.

With the integrated Cadence RTL-to-signoff flow, Efinix engineers were able to achieve first-pass success across a spectrum of nodes down to ten nanometres. Based on Efinix’s successful collaboration with Cadence, the company plans to continue its use of the Cadence flow to grow its Trion product line.

The Efinix Trion product family offers its customers improved power, performance and area (PPA), and therefore they required advanced power and area optimisation algorithms that support a variety of nodes. The Cadence digital full flow solution addressed Efinix’s requirements and provided the following benefits:

  • Design implementation and optimisation: Cadence provides a unified physical optimisation flow from RTL to GDSII with a common UI and database, allowing Efinix to have a seamless transition from physical synthesis to implementation
  • Optimal signoff convergence: The Cadence digital full flow is a digital flow solution with fully integrated place and route, timing signoff and IR drop/power signoff technologies, enabling Efinix to achieve faster design closure with fewer iterations to speed time to market

“We’re dedicated to continuous innovation, ensuring our Trion family of FPGAs for edge compute, AI/ML and vision processing segments meet the highest industry standards for excellence,” said Tony Ngai, founder, CTO and SVP of engineering at Efinix. “Through our collaboration with Cadence and with the strength of their digital full flow solution, we were able to deliver the first wave of Trion family FPGAs in two years, from design start to mass production, successfully optimising for the smallest silicon geometries to provide our customers with the best PPA.”

The Cadence digital full flow solution features the Genus Synthesis Solution, Innovus Implementation Solution, Tempus Timing Signoff Solution, Quantus Extraction Solution and Voltus IC Power Integrity Solution. The flow supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence and delivering better predictability.

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