The device is a 14-bit 5.7 Giga Samples Per Second (GSPS) DAC and a 12-bit 4.0 GSPS ADC. Based on a quad-switch architecture that enables dual-edge clocking operation, the DAC core increases the DAC update rate to 5.7 GSPS when configured for Mix-Mode or 2x interpolation. The input sampling clock can be via the front panel or the on board wide-band PLL. The FMC225 has a trigger input which is routed to the FMC connector. The analogue input/output, clock input and trigger inputs are routed via SSMC connectors.
FPGA Mezzanine Card is both an ADC & a DAC
An FPGA Mezzanine Card (FMC), which is both an ADC and a DAC, has been introduced by VadaTech. Compliant to the VITA 57 specification, the FMC525 meets Radar, LTE/Broadband communications systems, ATE, physics and video/broadcast requirements.