Displays

Evatronix Adds the Scaling Capabilities to its PANTA DP20 Display Processor

19th February 2013
ES Admin
Evatronix SA has announced the new version of the advanced display processor, PANTA DP20, which now features scaling capabilities provided by a separate, yet easily integrable PANTA CP10 coprocessor. Utilizing latest ARM technology like TrustZone and AXI4 the PANTA DP20 is targeted specifically at high-end mobile/portable products, like smartphones and tablets, with ultra-low power consumption and impressive processing performance.
There are two scaling algorithms implemented in the PANTA CP10 so that user can choose the best one for his application. For both methods there are plenty of configurable parameters that can further optimize the scaling process. The main scaling algorithm in the PANTA CP10 is based on polyphase multi-tap filtering, and utilizes 6-tap and 16-phase filters. Input and output resolutions are register programmable in the design together with a set of filter coefficients.

EXAMPLE APPLICATION
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An example application is a graphics subsystem which utilizes the PANTA DP20 display processor equipped with the PANTA CP10 scaling coprocessor. In this case the GPU is responsible only for rendering graphics layer pixels and sending them to the frame buffer, being reliefed from the following operations: YUV to RGB conversion, alpha-blending and scaling. These are now handled by the PANTA DP20 and CP10 units in the most efficient way.

In the presented system, the video layer converted by the PANTA DP20 to the RGB format is composed with the other graphics layers and directly displayed on the external panel. At the same time the composed frame is down-scaled from 1080p to 720p by the PANTA CP10 module and forwarded directly to the composition module of the DP20 IP. Thanks to the PANTA CP10 scaling capability this power-consuming operation is not executed in the GPU and therefore the overall SoC power consumption significantly decreases.

Total power consumption of PANTA components presented in this use case and implemented in the 40nm LP process is less than 30 mW

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