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Xilinx Improves Design Flow for Industry's Only Proven Partial Reconfiguration FPGA Technology with ISE Design Suite 12.2

4th August 2010

Xilinx

ES Admin

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Xilinx announced the availability of its fourth generation partial reconfiguration design flow and new improvements to its intelligent clock gating technology that deliver a 24 percent reduction in dynamic block-RAM (BRAM) power consumption in Virtex(R)-6 FPGA designs. Designers can download ISE(R) Design Suite 12.2 today to take advantage of an easier-to-use, intuitive partial reconfiguration design flow as well as take further steps to reduce power consumption and reduce overall system costs. In addition, a low-cost simulation solution for the embedded design flow is also now available in the latest release of the ISE Design Suite.

As systems become more complex and designers are asked to do more with less, the adaptability of FPGAs, in addition to their inherent reprogramability, has become a critical asset, said Tom Feist, senior marketing director, ISE Design Suite. Xilinx FPGAs have long supported partial reconfiguration and the flexibility to perform on-site programming and re-programming. Today, however, the severity of the constraints on cost, board space and power consumption requires exceptionally efficient and economic design strategies to compete, which is why we've made the design flow easier.

Partial Reconfiguration enables on-the-fly flexibility that can dramatically expand the capabilities of a single FPGA. While operational, designers can reprogram regions of the FPGA with new functionality without compromising the integrity of the applications running in the remainder of the device. For example, customers developing wired Optical Transport Network solutions can achieve multi-port multiplexer/transponder capabilities using 30-45 percent fewer resources, whereas Software Defined Radio solutions can dynamically exchange communication waveforms at the same time as other waveforms continue to operate without interruption and the need for bigger or additional components. Partial Reconfiguration also enables designers to manage power consumption by swapping out high-power consuming functions for more power-efficient functions when the highest performance is not required.

Xilinx made its fourth generation Partial Reconfiguration easier to use with a more intuitive design flow and interface. This includes an improved timing constraint and timing analysis flow, automatic insertion of proxy logic to bridge static and reconfigurable partitions, as well as full-design timing closure and simulation capabilities. ISE Design Suite 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for Partial Reconfiguration applications.