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Flexras Technologies Announces Breakthrough Automatic Partitioning Tool that Boosts FPGA-Based Prototyping Performance by 10X

29th May 2012

Flexras Technologies

ES Admin

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Flexras Technologies today announced Wasga Compiler, a software tool that boosts multi-FPGA design performance. Wasga Compiler is unique and is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.

Wasga Compiler automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time. It maximizes prototyping system performance and solves hardware/software validation bottlenecks of next generation SoCs to help meet the time-to-market challenges.

“Multi-FPGA platforms are heavily used for ASIC and SoC rapid prototyping. Existing tools notoriously fail the complex partitioning challenge. Verification engineers still rely on a cumbersome manual partitioning methodology,” remarked Hayder Mrabet, Flexras’ CEO. “Wasga Compiler complements FPGA-based SoC prototyping with high performance automatic partitioning. Engineers benefit from high clock frequencies, fast execution time, and unlimited design capacity. Wasga Compiler just makes the multi-FPGA designer’s life easier.”

Flexras will demonstrate Wasga Compiler at DAC Booth #2810 9am-6pm, June 4-6, 2012, Moscone Center, San Francisco.

FPGA-Based ASIC Prototyping
Wednesday, June 6, 2012 from 12:30pm-1:30pm, Room 105 (Exhibit Floor)
Co-authored by Flexras and Xilinx, this paper covers how the Wasga Compiler supports the latest Virtex-7 multi-die FPGAs for ASIC and SoC Rapid Prototyping.

The Wasga Compiler is available now, for pricing contact Flexras Technologies.