Design

Verification system certified for Samsung Foundry

20th April 2021
Alex Lynn

Cadence Design Systems, has announced that the Cadence Pegasus Verification System has achieved certification for Samsung Foundry’s 5nm and 7nm process technologies. Through the collaboration with Samsung Foundry, the Cadence physical verification flow has been optimised to enable customers using Samsung Foundry’s advanced nodes to reach signoff accuracy and runtime goals in a variety of market areas, including the mobile and hyperscale markets.

Samsung Foundry also delivered an enhanced, signoff-accurate process design kit (PDK) to facilitate the adoption of the Pegasus Verification System on the Samsung 5nm and 7nm technologies.

The Pegasus Verification System offers many advantages for engineers creating designs using Samsung’s advanced nodes. It provides massive scalability, which leads to faster turnaround times and more predictable design cycle times with design rule checks (DRCs), layout versus schematic (LVS), hierarchical metal fill (HMF) insertion and design-for-manufacturing (DFM) signoff.

It has been validated with the Cadence Innovus Implementation System, providing improved productivity with signoff-level checks through implementation. Designers can easily fulfill mandatory DFM signoff requirements by leveraging integrated hotspot detection with seamless automated fixing. Additionally, the Pegasus Verification System features a tight, interactive integration with the Cadence Virtuoso Layout Suite environment.

“We value our collaboration with Cadence and have worked diligently to enable our mutual customers to sign off their designs using the Pegasus Verification System and Samsung Foundry’s advanced-node process technologies,” said Jong-Wook Kye, Vice President of the Design Enablement Team at Samsung Electronics. “Through the certification process, we’re enabling our mutual customers to simultaneously improve power, performance and area and accelerate their design cycles to handle extreme market pressures. We also found that the Pegasus Verification System provided massive scalability for faster iterations, which lets customers focus on improving design closure.”

“The Pegasus system was architected from the ground up to accelerate the signoff physical verification flow through its massively parallel capabilities and integration into our Virtuoso environment and Innovus Implementation System,” said Michael Jackson, Corporate Vice President, R&D in the Digital & Signoff Group at Cadence. “This allows our customers to define and meet design schedules with greater predictability. We appreciate our continued collaboration with Samsung Foundry, which is critical to ensure our customers are confident using our signoff flow on Samsung’s advanced 5nm and 7nm process technologies.”

The Pegasus Verification System is part of the broader Cadence digital flow, which provides better predictability and a faster path to design closure and supports Cadence’s Intelligent System Design strategy, enabling SoC design excellence.

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