Verification platform delivers 2X design compilation capacity

8th May 2019

Mick Elliott

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The verification market is growing as it represents more and more of the costs of chip design, and as processes move deeper into sub-micron territory, costs could be up to 80% for designers using 5nm nodes. To meet this challenge Cadence Design Systems has unveiled the third generation of its Jasper Gold Formal Verification Platform, featuring machine learning technology and core formal technology enhancements.

According to Pete Hardee, Director, Product Management, Formal Solutions, this latest release delivers a two times capacity increase and 50% memory footprint reduction.

It incorporates Smart Proof Technology to improve verification throughput for all JasperGold apps. Machine learning is used to select and parameterise solvers to enable faster first-time proofs. Additionally, machine learning is used to optimise successive runs for regression testing, either on premises or in the cloud.

With Smart Proof Technology, proofs speed up by up to 4X, and up to 6X on regression runs.

“We measured averages of 2X faster proof performance out of the box and 5X faster regression runs across our design test cases with the JasperGold platform,” stated Mirella Negro Marcigaglia, Digital Design Verification Manager at STMicroelectronics. “We are also seeing non-converged properties reduced by over 50%. Combined, these improvements significantly boost our verification productivity.”

Given today’s larger and more complex SoC designs, the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis.

Engineers can effectively scale design capacity through advanced parallel compilation technologies that optimally use available compute resources, and by running proofs on the Cloud.

The platform’s new formal coverage technologies let engineers perform IP signoff purely within the JasperGold platform. These formal signoff technologies include improved proof-core accuracy, new techniques to derive meaningful coverage from deep bug hunting and new formal coverage analysis views.

Together those features deliver signoff-quality formal coverage metrics and enable multi-engine chip-level verification closure.

The JasperGold Formal Verification Platform, part of the Cadence Verification Suite, offers comprehensive coverage in the vManager Metric-Driven Signoff Platform, which combines JasperGold formal results with Xcelium simulation and Palladium emulation metrics to speed overall verification closure.

It supports the company’s System Design Enablement strategy, which enables systems and semiconductor companies to create complete, differentiated end products more efficiently.

The Cadence Verification Suite is comprised of the best-in-class JasperGold, Xcelium, Palladium and Protiumcore engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.