Design

Verification IP at chip level enables efficiency gains

13th October 2020
Mick Elliott

Cadence Design Systems has released Cadence System-Level Verification IP (System VIP), a new suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis.

“It brings verification IP to the chip level,” says Moshik Rubin (pictutred), Product Management Group Director, System & Verification Group at Cadence. “Using Cadence System VIP, customers creating complex hyperscale, automotive, mobile and consumer chips can improve chip-level verification efficiency by up to 10X.”

Rubin points to the progression from single core processors to today’s multi-core, heterogeneous engines where power and performance is based on use case.

Tests created using the Cadence System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up.

Cadence System VIP consists of four new tools and libraries:

  • System Testbench Generator: Allows users to automatically generate SoC testbenches with complex memory, cache, interface and bus configurations
  • System Traffic Libraries: Provide users with a rich portfolio of pre-defined tests that can be plugged into a System VIP testbench, including coherency, performance, PCI Express (PCIe) and NVMe subsystems
  • System Performance Analyser: Offers comprehensive performance analysis reporting and visualisation for memory subsystems, interconnects and peripherals
  • System Verification Scoreboard: Provides comprehensive data and cache-coherency checks across coherent interconnects, memories and peripherals

“Through our collaboration with Cadence, we’ve reduced some of the complex SoC verification challenges, especially around I/O peripherals,” said Tran Nguyen, director of Design Services at Arm. “By using Cadence System Traffic Libraries and System Performance Analysers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”

The Cadence System VIP tool suite is part of the broader Cadence Verification Suite and supports the company’s Intelligent System Design strategy. The Cadence Verification Suite is comprised of core engines and smart verification technologies that increase verification throughput and design quality, fulfilling verification requirements for a wide variety of applications and vertical segments.

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