Design

VadaTech VPX572 provides dual ADC with sampling rates

2nd July 2020
Alex Lynn

VadaTechhas announced the VPX572. The VPX572 provides a dual ADC with sampling rates of up to 6.4 GSPS at 12-bit resolution (ADC12DJ3200).

The ADCs are capable of being configured to run as quad channel each running at 3.2 GSPS. The XCVU13P FPGA has large 360 Mb on-chip UltraRAM which is excellent for applications such as radar simulation and smart jamming. The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE or Aurora backplane connections. There are also general purpose I/O signals, e.g. for trigger, routed to the front panel, which also contains 8 bi-color user LEDs.

The ADCs on the VPX572 have a common sampling rate, which can be fed from front panel (Direct RF Clock) or from PLL locked to a 10/100 MHz reference clock sourced from front panel or backplane. The ADCs are fully coherent with sampling clock selection being by ordering option.

The board also includes board health management/monitoring capability using VadaTech’s field-proven IPMI software, compatible with our tier 2 platform managers.  An on-board management controller has the ability to access board sensors and manage FPGA image updates.

The unit is available in a range of temperature, shock and vibration specifications per ANSI/VITA 47, up to V3 and OS2.

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