Ultra-low jitter single channel network synchroniser clock

The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronisation options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001-ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave).

The DPLL can phase-lock to a 1-PPS (pulse-per-second) reference input and support optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimise output clock disturbance when a loss of reference (LOR) occurs.

The device can use a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronisation standards. Otherwise, the device can use a standard XO when free-run or holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power up with the internal EEPROM or ROM. The EEPROM is factory pre-programmed and can be programmed in-system if needed.

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