Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing

“PCI-SIG is the industry leading organization responsible for development and management of the PCI Express specification,” said Al Yanes, president and chairman, PCI-SIG. “We are delighted that Cadence continues to advance the PCI Express 3.0 specification with their innovative verification IP products and methodologies.”

The growing complexity of standard interfaces, typified by high speed interconnects such as the PCI Express 3.0 standard and cache coherent SoC fabrics such as AMBA 4 AXI Coherency Extensions (ACE), make them increasingly difficult to verify. TripleCheck IP Validator addresses this issue by building on the earlier generations of Cadence compliance solutions: PureSuite and Compliance Management System (CMS). TripleCheck combines features of both solutions plus significant new capabilities.

“Feedback from hundreds of users over several years was used to shape TripleCheck,” said Erik Panu, vice president of research and development for Verification IP, System and Software Realization Group, Cadence. “Customers wanted the extensive directed tests that PureSuite provided, plus the constrained-random testing approach of CMS and its innovative vPlan, an interactive verification specification that correlates coverage from regression runs to the protocol specification, all based on the Universal Verification Methodology (UVM).”

IP Validator is currently available for PCIe Gen 3, and Cadence has support for several additional protocols in development for release later this year. Its test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages.