Design

Timing signoff tools enables 400Gbps PAM4 SoC on 16FF process

12th December 2018
Alex Lynn

It has been announced by Cadence Design Systems that MaxLinear has used Cadence timing signoff tools to successfully deliver the MxL935xx Telluride device, a 400Gbps PAM4 system on chip (SoC) using 16FF process technology. The Cadence Quantus Extraction Solution and Tempus Timing Signoff Solution were key enablers of the on-time delivery of working silicon for MaxLinear.

The Telluride device is the key component for system vendors to be able to develop a 400Gbps optical interconnect module in a compact form factor for intra-datacenter applications with a transmission distance up to two kilometres.

The Cadence timing signoff tools provided MaxLinear with the ability to manage congestion throughout every stage of the design flow, from placement to signoff, with a target of lowering design density, allowing for high target utilisation and cost tradeoffs involving using more layers versus chip area. The Cadence timing signoff tools provided MaxLinear with a trusted, reliable design flow for fast runtimes, signoff accuracy, and first-pass engineering change order (ECO) fixes to achieve on-time tapeouts.

MaxLinear estimated that they were able to get two times faster multi-corner extraction runtimes versus single-corner runs and three times faster timing signoff flow with the Quantus and Tempus solutions. MaxLinear was able to fix over 90% of hold violations with Tempus ECO, which reduced their iterations to only three to four ECOs while fixing across 18 timing views.

The Tempus physically-aware ECO flow helped MaxLinear to dramatically reduce the overall ECO cycle. The key to the fastest convergence and reduction in iterations for on-time tapeout was the fact that both the Innovus Implementation System and Tempus ECO solution use the same signoff extraction and STA engines for optimisation and signoff.

“Managing heavily congested and high-speed SoC design throughout the design flow with high-target utilisation to reduce costs at 16FF node is a challenging task,” said Dr Paolo Miliozzi, VP of SoC Technology, MaxLinear. “We are able to deploy the full-flow Cadence digital and signoff tool set including their Quantus, Tempus, and Tempus ECO solutions for successful signoff and on-time tapeout. Using these signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.”

MaxLinear used the Cadence full-flow digital solution including Genus Synthesis Solution, Innovus Implementation system for place and route, Quantus Extraction Solution and Tempus Timing Signoff Solution. Cadence provides tightly integrated tools with unified algorithms, engines and data models, as well as a common user interface throughout the entire digital design process.

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