Design

Tensilica SoC using adaptive body bias feature

26th March 2021
Alex Lynn

Cadence Design Systems has announced that it has collaborated with GLOBALFOUNDRIES (GF) to successfully tape out a Cadence Tensilica test chip on GF’s 22FDX platform. This design used the Cadence digital full flow with Adaptive Body Bias (ABB) foundation IP along with the popular Cadence Tensilica HiFi 5 and Fusion F1 DSPs, which are suited for high-growth markets including IoT, voice processing and always-on sensor fusion.

The test chip produced the desired results, demonstrating ultra-low power and ultra-low voltage. The Tensilica HiFi 5 and Fusion F1 DSPs and the digital full flow support Cadence’s broader Intelligent System Design Strategy, enabling SoC design excellence.

GF’s 22FDX platform is a proven solution for a range of applications, including single-chip radio frequency (RF) and mixed-signal SoCs, which is a logical fit for Tensilica IP. The Tensilica HiFi 5 DSP is for artificial intelligence (AI) speech and audio processing, making it suited for digital assistants, infotainment and other voice-controlled products. The Tensilica Fusion F1 DSP efficiently runs the narrowband communications standards typically associated with IoT communications, such as Bluetooth Low Energy, Thread and Zigbee, WiFi and global navigation satellite systems (GNSS).

The digital full flow incorporates unified implementation and timing- and IR-signoff engines, offering enhanced signoff convergence, reduced design margins and iterations, optimal power, performance and area (PPA) and improved throughput. The Cadence full flow with integrated signoff achieves convergence by concurrently closing the design for all physical, timing and reliability targets. For designers who want to combine digital, RF, mixed-signal and custom designs on the same 22FDX chip, GF offers a Cadence-based mixed-signal OpenAccess process design kit (PDK) to improve productivity.

The Cadence digital flow used for the tapeout on GF’s 22FDX platform included the Genus Synthesis Solution, Innovus Implementation System and Modus DFT Software Solution for implementation as well as the Tempus Timing Signoff Solution, Tempus ECO Option, Quantus Extraction Solution and Voltus IC Power Integrity Solution for full timing and power signoff.

“Cadence’s ongoing collaboration with GF to provide premier solutions to our joint customers has resulted in this compelling full-flow tapeout proof point with extremely attractive Tensilica DSP power, performance and area metrics,” said Sanjive Agarwala, Corporate VP, R&D, IP Group at Cadence. “Customers building products in the high-growth audio, voice, sensor fusion and communications markets can benefit by achieving highly efficient energy results, very low voltages and reduced project times with our digital flow and Tensilica HiFi 5 and Fusion F1 DSPs on GF’s 22FDX platform.”

With its high performance, power consumption, and broad feature integration capability, GF’s differentiated 22FDX platform is the solution of choice for designers and innovators working in IoT, wearables, Edge AI and other exciting applications.

“This tapeout validates the performance of the Cadence digital flow and Tensilica DSPs in conjunction with ABB enablement, which is a key differentiator for customers using our 22FDX platform,” said Mark Ireland, Vice President of Ecosystem and Design Solutions at GF. “The Tensilica DSPs’ compelling PPA results with drain power voltage down to 0.5V are increasingly important to our customers designing portable devices that demand the extreme energy efficiency offered by our 22FDX solutions.”

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