Circuit blocks such as oscillators can be simulated at high level, enabling incompatibilities with other parts of the system to be identified early in the design process. This saves design time and cost, and encourages better design practice. Furthermore, while C programming can take years to master, users who are knowledgeable about the devices they are trying to model can learn to use Verilog-A in a short time. This means that more in-house model development and simulation will be possible, avoiding the expense and delays associated with using external contractors. Verilog-A models are well standardised, allowing portability across simulators from all major EDA vendors.
T-Spice Pro operates under Microsoft Windows. It generates fast and accurate simulations of analogue and mixed-signal IC designs. The tool can read HSPICE® and P-Spice® netlist formats directly and includes a Simulation Manager and device modelling functions. T-Spice Pro already offers support for Penn State Philips Model (PSP), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC and MEXTRAM. Custom models can be created using algebraic expressions for voltage and current controlled sources, data from external tables, or the C programming language. The addition of Verilog-A support makes the simulator significantly more versatile and productive.
HiPer Simulation will be available in Q1, 2008 priced at $11,500. Verilog-A support will be bundled with Tanner’s complete design flow package, HiPer Silicon, at no additional cost.
A beta version of HiPer Simulation is being trialled with some of Tanner’s existing customers from December 1, 2007.