Design

Synopsys Redefines the IP Supplier Paradigm with New IP Accelerated Initiative

26th June 2014
Jacqueline Regnier
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Synopsys, Inc announced the IP Accelerated initiative to help designers significantly reduce the time and effort of integrating IP into their system-on-chips (SoCs). This initiative augments Synopsys' established broad portfolio of silicon-proven DesignWare IP with the addition of new IP Prototyping Kits, IP Virtual Development Kits and customized IP subsystems to accelerate prototyping, software development and integration of IP into SoCs. With the IP Accelerated initiative, Synopsys goes beyond the traditional IP supplier paradigm, redefining what customers can expect from their IP providers to help them successfully integrate IP with less effort, lower risk and faster time-to-market.

With the increasing SoC hardware and software complexity, developers need more from their IP providers to help meet their project schedules. Traditional IP blocks alone are no longer adequate to address the growing SoC design and integration challenges. Designers require solutions that ease IP configuration and integration into the overall SoC as well as accelerate their software development effort. The Synopsys IP Accelerated initiative delivers solutions that address designers' pain points during IP implementation, software development and IP integration.

"Due to increasing design complexity, escalating design costs and shorter time-to-market, usage of third-party IP is expected to more than double from 2012 to 2018," said Richard Wawrzyniak, senior market analyst, ASIC and SoC at Semico Research Corporation. "More companies are turning to third-party IP providers, such as Synopsys, to provide comprehensive solutions such as those offered by the IP Accelerated initiative to lower their development cost, reduce integration risk and meet their market schedules."

DesignWare IP Prototyping Kits

The DesignWare IP Prototyping Kits center around proven reference designs that enable designers to start implementing the IP in an SoC context in minutes. The IP Prototyping Kits provide the essential hardware and software elements needed to reduce IP prototyping and integration effort, including Synopsys' HAPS®-DX FPGA-based prototyping system with pre-configured IP and SoC integration logic, a PHY daughter board, simulation testbench and a DesignWare ARC® processor-based 32-bit software development platform running Linux, reference drivers and application examples. Designers can modify the standard IP configuration for their target application through a fast iteration flow consisting of Synopsys' coreConsultant IP configuration tool, Synopsys' ProtoCompiler synthesis and debug tool, and compilation scripts.

"With 50 percent of our budget going to software development, it's necessary for us to have deeper system expertise to better support our customers," said John Cummins, senior vice president, worldwide sales and marketing at DisplayLink. "We need to focus not only on acquiring the individual IP blocks, but also how the IP is integrated and validated in the context of the entire SoC. Synopsys' IP Accelerated initiative hits the mark by addressing the key needs that directly impact companies' ability to develop software for the IP and integrate it into an SoC."

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