Combined with Synopsys’ DFTMAX compression, this new test technology will enable design teams to meet their test quality, time and cost goals with unprecedented speed.
“Increasingly complex SoC designs and shrinking schedules require fast turn-around for generating high-quality manufacturing test patterns,” said Roberto Mattiuzzo, SoC integration and DFT methodologies manager in STMicroelectronics’ Digital and Mixed Processes ASIC division. “Working with Synopsys on their new ATPG technology should produce faster ATPG run times and significantly fewer test patterns to help us test first-silicon samples sooner and minimise time on the tester. This technology will also help accelerate our ramp-up of dense and complex products in FD-SOI technology thanks to an even more efficient flow for our ASIC customers.”
The new test generation, fault simulation and diagnosis engines are extremely fast, exceedingly memory efficient and highly optimised for generating patterns and executing fine-grained multithreading of the ATPG and diagnosis processes.
These innovations lead to fewer test patterns and 10X faster runtime, enable utilisation of all server cores regardless of design size and surpass previous technologies that are limited by high memory usage.
Moreover, tight links with Synopsys’ Galaxy Design Platform tools, such as Design Compiler RTL Synthesis, PrimeTime timing signoff and StarRCT parasitic extraction, along with other Synopsys tools, including Yield Explorer yield analysis and Verdi automated debug system, deliver the highest quality test while minimising turnaround time.