Synchronisation of giga-sample ADCs for phased array radar systems

26th September 2019
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This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronised together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. 

The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analysed, showing synchronisation within 50ps without characterised cables or calibrated propagation delays.


  • Demonstrates a typical phased array radar sub-system by showing synchronisation of JESD204B giga-sample ADCs.
  • The LMK04828 clocking solution used is described in detail.
  • Test results show synchronisation within 50ps without any characterisation of cables or calibration of propagation delays.
  • Xilinx firmware development is discussed to offer a clear understanding of the requirements.
  • This sub-system is tested and includes example configuration files.

To learn more, click here.

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