The lastest version of BugHunter also offers a unique method of tracing backward through cause-effect relationships between simulation variables in Verilog designs that enables designers to debug down to the root cause of errors in their design. Cause-effect relationships are shown through a graphical tree rooted on the suspect variable. Users can expand downwards through this tree to see which statements in the code have contributed to the variable’s current value.
SynaptiCAD’s BugHunter Supports 64-bit ModelSim & Incisive Simulators
SynaptiCAD has released an updated version of it’s VHDL and Verilog testbench generation and debugging tool, BugHunter Pro, with support for 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators. Other new features include faster waveform capture (so simulations run 8x faster while being debugged), new methods for fast searching through the design hierarchy tree, support for capturing waveform data from VHDL types such as enums and time values, and functions for quickly changing the scoping level when using interactive debug commands.