Design

Structured ASIC Family with Embedded IP

19th January 2006
ES Admin
The CX6000 family of Structured ASICs from ChipX is fabricated in a high performance, eight-metal 0.13-µm process, and is said tothe accelerate time-to-market and reduces risk by integrating silicon proven IP subsystems into the Structured ASIC fabric.
The first twelve devices available in this product family, the CX6200 series, integrate an industry-standard PHY for USB 2.0 hi-speed On-The-Go (OTG) applications. ChipX will supply a single-cycle per clock instruction 80515 processor capable of up to 200MHz operation, and a USB controller proven to work with the PHY to customers through IP partnerships. The combination of PHY and Controller has achieved USB-IF compliance in silicon.

“Normally, designers seeking to build USB capability into an ASIC must purchase a PHY, a controller, and a processor, integrate them into their design, develop the software, then run the entire solution through compliance testing,” explains Elie Massabki, Vice President of Marketing with ChipX.

“This process is arduous, time-consuming and full of risk, since the various IP blocks may not communicate well. By providing our customers with a complete, compliance-capable solution, we can reduce their chip integration effort, shorten their development cycle and maximize their chance of design success.”

The CX6200 series is ideal for PC peripheral, imaging, consumer, security and a variety of industrial applications.

The CX6000 family uses ChipX’ silicon-proven X-Cell™ architecture. The highly granular and efficient architecture delivers higher gate densities and much lower device costs when compared to programmable devices in smaller geometries. This ChipX product family can be customized in 2, 3 or 4 layers of metal depending on the customer’s priority in terms of density and time to market. The CX6000 family is also equipped with configurable I/Os, capable of a wide range of capabilities including LVTTL, LVCMOS, SSTL18/2/3, HSTL, LVDS, LVPECL, XOSC, PCI, PCIX and double data-rate. The I/Os can be programmed with a number of parameters and can be individually configured as input, output, bi-directional, power or ground.

The new CX6200 product line offers 140k to 1.8M ASIC gates, up to 1.2 Mbits of embedded high-density SRAM and a maximum operating frequency of 250 MHz. It also adds four configurable, low-jitter PLLs with output frequency from 10 MHz to 1 GHz.

Tested prototypes can be delivered in as little as 4 weeks. CX6200 device prices start at under $5 in 100,000 unit volume.

Featured products

Upcoming Events

View all events
Newsletter
Latest global electronics news