Toshiba Announces Availability of Structured ASICs for European Customers
Toshiba Electronics Europe has announced the European availability of a Structured Array technology. The technology provides an ASIC alternative to FPGA with lower cost and power consumption - but still at significantly lower implementation and sample/production turn-around time than standard ASICs.Base
SoCs created using Toshiba’s Structured Array technology offer reduced costs, lower power consumption and, if required, higher performance than FPGA alternatives. Structured array designs can be developed with verified RTL data from an FPGA and support FPGA compatibility in terms of memory and I/O architecture. In addition, FPGA package and pin layout compatibility supports “drop-in” replacement for FPGA components.
The new Structured Arrays use a 65nm process technology and support up to 30 million raw logic gates, 20Mbit of SRAM and a maximum of 1200 I/O pins. LVDS and DDR capabilities are available and options for Gigabit high-speed transceivers (up to 6.5Gbps) are being developed. A 40nm line-up is also under development, targeting high-speed transceivers up to 12.5Gbps.
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